(1) Field of the Invention
The invention relates to a method of fabricating silicon structures, and more particularly, to the formation of shallow trench isolations for use with borderless contacts in integrated circuit devices.
(2) Description of the Prior Art
In the art, there are two conventional methods for forming such isolation regions. First, a thick layer of silicon oxide may be grown into the surface of the substrate through the process known as local oxidation of silicon (LOCOS). Second, trenches may be etched into the substrate surface and then filled with silicon oxide. This method is called shallow trench isolation (STI).
Although LOCOS has long been the most prevalent technique used to form isolation regions between active areas, recently, shallow trench isolation has gained popularity. Although most STI approaches require more processing steps than LOCOS, the use of STI is growing because of two distinct advantages. First, STI can allow for the formation of narrower isolation regions. Second, STI structures have a flatter topology. Both of these advantages facilitate greater device and interconnect density for integrated circuit devices.
Doped junctions are formed in the silicon substrates of integrated circuit devices in the active areas between the isolation regions. Traditionally, in the art, contacts to these doped junctions in the silicon substrate have required a substantial area penalty. Design rules require that the active areas significantly overlap the contact openings. This large overlap guarantees that the contact etch does not etch any of the field isolation oxide. Damage to the field oxide adjacent to the doped junction could result in excessive leakage currents and reduced device yield. In addition, the topology of the field oxide regions poses problems with the metal layer fill of the contact opening, and subsequently, with the contact resistance.
With the advent of the use of shallow trench isolations (STI), it is possible to reduce the spaces between active devices. In addition, to further reduce the area used for each integrated circuit device, another technique, called borderless contacts, has become increasing useful in the art. In a borderless contact, the contact opening actually extends beyond the edge of the device active area and over the shallow trench isolation.
Referring to FIG. 1, a cross-section of a partially completed prior art integrated circuit is shown. Trenches have been etched in a silicon substrate 10. The trenches have been filled with silicon oxide 14 and planarized to form shallow trench isolations.
Referring to FIG. 2, a typical MOSFET transistor has been formed with a gate electrode 18 and source-drain junctions 22. An interlevel dielectric layer 26 has been deposited overlying the substrate and the MOSFET transistor. The interlevel dielectric layer 26 is typically comprised of a silicon oxide based material.
Referring to FIG. 3, contact openings have been etched in the interlevel dielectric layer 26 for the source and drain junctions 22. Note how the contact openings extend out from the junctions 22 and overlap the shallow trench isolations. Such a placement of the contact openings illustrates the concept of the borderless contact.
The illustration of FIG. 3 also shows a common problem in the art. The contact etch is typically a reactive ion etch (RIE) specific to silicon oxide. Unfortunately, both the interlevel dielectric and the shallow trench isolation are composed of silicon oxide. It is essential to completely etch the contact opening so that there are no contact resistance problems. Unfortunately, it is difficult to completely etch the contact opening without also over etching a portion of the shallow trench isolation 30.
Referring to FIG. 4, after the barrier layer 34 and metal layer 38 are deposited and the contacts are defined, the circuit is completed. Where such over etching 30 occurs, a potential source of junction leakage currents exists. Such leakage currents can significantly reduce device yield.
Several prior art approaches deal with over etch problems and with borderless contacts. U.S. Pat. No. 5,821,153 to Tsai et al discloses a process to reduce LOCOS field oxide etch loss by forming an oxynitride layer over and under the field oxide. U.S. Pat. No. 5,268,330 to Givens et al teaches a method to improve transistor gate sheet contact resistance. A silicon nitride layer is deposited overlying the transistor and acts as an etch back stop during intermetal dielectric planarization. A borderless contact is also disclosed where a silicon nitride layer must be etched through to contact source and drain junctions. However, the silicon nitride layer does not prevent shallow trench isolation oxide loss during the contact etch. U.S. Pat. No. 5,466,636 to Cronin et al discloses a method to form borderless contacts where a removable mandrel is used to protect regions. In this invention, the mandrel layer is formed after transistor definition. U.S. Pat. No. 5,674,781 to Huang et al teaches a borderless contact process. U.S. Pat. No. 6,165,871 to L. E. Hur et al issued on Dec. 26, 2000 teaches a process for forming a self-aligned nitride spacer which acts as an etch stop for borderless contact formation.